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m arker 1 2. 931 ghz ch1 s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz 1 1 - 2. 997 db 2. 931 ghz s ch2 11 l og mag ref 0 db 10 db / 2 2 - 15. 000 db . 949 ghz m arker 2 0. 949 ghz d d elay l l ine d d ata b b ook
t t able of c c ontents contents ............................................................................................. 2 introduction ........................................................................................ 3 definitions .......................................................................................... 4 delay line test methods ................................................................... 5 high frequency delay lines single in line dl1 series ..................................................... 6-7 surface mount gl1 series .................................................... 8-9 surface mount gl2 differential series ............................. 10-11 intermediate frequency delay lines single in line ds1 series .................................................. 12-13 chip delay line cl series .............................................................. 14 bandwith considerations ................................................................. 15 complimentary products positive emitter coupled logic (pecl) terminator .............. 16 calibration standards .............................................................. 17 footprint layouts ............................................................................. 18 notes ................................................................................................. 19 world wide sales offices ................................................. back cover copyright ? by thin film technology 1999 published by the p h ilter c i rcuits division, 1980 commerce drive, n. mankato, mn 56003 all rights reserved. this book, or parts thereof, may not be reproduced in any form without permission. printed in the united states of america. t t hin f f ilm ilm t t echnology echnology . . d d elay elay l l ines. ines. because because t t iming is everything. iming is everything. tm tm
the component needs for future systems design will be met with higher technology. thin film technology. h h igh speed system design needs full wave regime implementation in order to maintain signal fidelity. harmonics not considered at slower speeds must be accounted for when fast rise times and high bandwidths are to be used. when edge rates and circuit speeds enter the sub-nanosecond regime, all components used in a system design must obey high speed design rules, whether they be pack- ages, devices, integrated circuits, interconnects, or printed circuit boards. t t hin film component design is uniquely appropriate for high frequency design: the precision of pattern features, purity of film, stability of substrate mate- rials, and advanced assembly technologies offer solutions for high speed design. wave propagation through correctly designed thin film elements provide for pre- cise impedance control, a reduction in capacitive and inductive parasitics, and elimination of ground bounce. shielded designs protect for electro-magnetic and radio-frequency interference. t t hin film technology corporation manufactures high speed delay lines based on microstrip, stripline, and multi-conductor transmission lines. available in leaded, surface mount, and chip configuration, these products have performance to 5 gigahertz. new designs and materials are under continuous development to extend this range. it is our philosophy that higher technology components can improve your system performance and lower your costs, both now and in the future. h h igh frequency measurement is essential to assure correct device char- acterization. attention to field patterns is necessary when representing transmis- sion lines in order to understand reflections, mismatches, and skin effects. test design layout should replicate the field patterns that will actually occur with the real package, so that accurate device characteristics represented by scattering para- meters can be made. proper calibration standards used at the device under test are sine qua non.
d d efinitions scattering parameters (s-parameters): a two port numbering convention used commonly at high fre- quencies relating to network measurements. the first number represents the port where the energy is emerging from the device and the second number is the port where the energy is entering the device. parameter s21: the forward transmission coefficient indicating the ratio of energy emerging from port 2 to the energy incident to port 1. parameter s11: the reflected transmission coefficient indicating the ratio of energy emerging from port 1 to the energy incident to port 1. time delay (td): the elapsed time from the 50% on the leading edge of the input pulse to the 50% point on the leading edge of the delayed pulse. network risetime and fall time(tr): the true measure of delayed pulse risetime performance expressed by the following: input risetime and falltime (tri and tfi): the time between the 10% and 90% of the input voltage. output risetime and falltime (tro and tfo): the time between the 10% and 90% of the output voltage. input and output voltage (ei and eo): the amplitude of the input and output voltages, respectively. attenuation (at): the difference in amplitude between input and output pulses. attenuation is caused pri- marily by the direct current (dc) resistance of the delay line. pulsewidth (pw): the time difference between the 50% point of the leading edge and the 50% point of the trailing edge of the pulse. pulse distortion (s): the maximum spurious % change, either positive or negative, relative to the pulse amplitude. pulse edge over/undershoot: (pos, nos): peak amplitudes occurring at either the top or bottom of the output pulse. tr = (t r output) 2 - (t r input) 2 ei 90% 50% 10% pw tri tfi td at pos s nos eo tro tfo incident transmitted s 21 reflected s 11 port 1 port 2 dut
d d elay l l ine t t est m m ethods f f requency d d omain m m easurement network analysis may be used to measure insertion loss, return loss, phase and group delay, with signal stimulus both forward and reverse to the device. for our passive delay lines, performance is indicated as loss in the frequency domain. the graphed information presented in this databook is labeled according to traditional scattering parameters (s-parameters). s 21 and s 11 on the following pages indicates insertion loss (energy incident but lost through the device) and return loss (ener- gy incident but reflected away from the device). the data is presented in summary form, but frequency performance data may be requested for specific part numbers. t t ime d d omain m m easurement high speed (rise time <55 ps) dig- ital signals are used to stimulate the device for rise time (tro) and fall time (tfo) performance. data is presented in the time domain, and is another measure indicating frequen- cy performance. sampling mea- surements can be used to demon- strate signal fidelity and can be processed by a variety of techniques. additionally, time domain reflectometry (tdr) measurements may be made to provide time delay performance as well as detailed impedance mapping of the device transmission structure. tdr measurements can be performed either in a single end driven mode, or in a dual end (differential) driven mode, which is necessary for the gl2l series differential delay line product.
dl dl s s eries d d elay l l ines dl1l5 ** *** s u.s. patent 4,641,113 26 m 26.5 max 4.50 2.54 7.62 0.5 0.1 4.20 0.2 0.25 7.60 2.54 dl1l5 series 50 ohm dl1l5wk010s 0.10 dl1l5wk020s 0.20 <0.2 ohm dl1l5wk030s 0.30 dl1l5wk040s 0.40 <200 ps <200 ps dl1l5wk050s 0.50 dl1l5xk060s 0.60 dl1l5xk070s 0.70 >4.5 ghz dl1l5xk080s 0.80 dl1l5xk090s 0.90 dl1l5xk100s 1.00 <0.4 ohm dl1l5xk110s 1.10 <250 ps <250 ps dl1l5xk120s 1.20 dl1l5xk130s 1.30 dl1l5xk140s 1.40 dl1l5xk150s 1.50 dl1l5xk160s 1.60 dl1l5xk170s 1.70 <300 ps <300 ps dl1l5xk180s 1.80 >2.5 ghz <0.6 ohm dl1l5xk190s 1.90 dl1l5xk200s 2.00 dl1l5xk210s 2.10 dl1l5xk220s 2.20 dl1l5xk230s 2.30 <350 ps <350 ps dl1l5xk240s 2.40 dl1l5xk250s 2.50 >0.9 ghz <1.0 ohm dl1l5xk260s 2.60 dl1l5yk270s 2.70 dl1l5yk280s 2.80 dl1l5yk290s 2.90 >2.0 ghz <400 ps <400 ps dl1l5yk300s 3.00 dl1l5yk310s 3.10 dl1l5yk320s 3.20 <1.2 ohm dl1l5yk330s 3.30 dl1l5yk340s 3.40 dl1l5yk350s 3.50 <450 ps <450 ps dl1l5zk360s 3.60 dl1l5zk370s 3.70 dl1l5zk380s 3.80 <1.4 ohm dl1l5zk390s 3.90 dl1l5zk400s 4.00 >1.5 ghz dl1l5zk410s 4.10 <500 ps <500 ps dl1l5zk420s 4.20 dl1l5zk430s 4.30 <1.6 ohm dl1l5zk440s 4.40 dl1l5zk450s 4.50 dl1l5zk460s 4.60 dl1l5zk470s 4.70 dl1l5zk480s 4.80 >1.0 ghz <550 ps <550 ps dl1l5zk490s 4.90 <2.0 ohm dl1l5zk500s 5.00 dl1l5zk510s 5.10 p/n td insertion loss return loss tro tfo dcrv (ns) (-3 db) (15 db) dimension mm application note: for precise high speed digital timing deskew, socket the delay line for custom timing adjustments against lot to lot propagation delay variations in ic devices. !
dl dl s s eries d d elay l l ines dl1l5 ** *** s u.s. patent 4,641,113 s 21 l og mag 5 db / ref 0 db start 0. 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 4. 935 ghz 1 1 - 3. 011 db 1 1 - 15. 006 db 1. 342 ghz m arker 1 s 21 l og mag 5 db / ref 0 db start 0. 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 2. 483 ghz 1 1 - 2. 996 db 1 1 - 15. 003 db m arker 1 0. 944 ghz s 21 l og mag 5 db / ref 0 db start 0. 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 1. 605 ghz 1 1 - 2. 996 db 1 1 - 15. 008 db 1. 193 335 400 ghz 1. 193 ghz m arker 1 s 21 l og mag 5 db / ref 0 db start 0. 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 1. 141 ghz 1 1 - 2. 994 db 1 1 - 14. 997 db 1. 133 ghz m arker 1 dl1l5xk100s 1 ns dl1l5xk200s 2 ns dl1l5zk500s 5 ns s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 2. 362 ghz 1 1 - 2. 993 db 1 1 - 15. 000 db m arker 1 0. 958 ghz dl1l5yk300s 3 ns dl1l5zk400s 4 ns characterization data is typical for this series of delay lines.
gl1 s gl1 s eries d d elay l l ines gl1l5 ** *** s u.s. patent 5,365,203 ms190s m 6.05 max 8.35 max 13.55 max 1.88 0.25 1.27 0.13 5.15 max 0.56 max 18 0.28 0.05 0.10 18 9 16 gl1l5 series 50 ohm gl1l5ls010s 0.10 gl1l5ls020s 0.20 gl1l5ls030s 0.30 gl1l5ls040s 0.40 >2.50 ghz >0.60 ghz gl1l5ls050s 0.50 <200 ps <200 ps <1.0 ohm gl1l5ls060s 0.60 gl1l5ls070s 0.70 gl1l5ls080s 0.80 gl1l5ls090s 0.90 gl1l5ls100s 1.00 gl1l5ms110s 1.10 >2.00 ghz gl1l5ms120s 1.20 gl1l5ms130s 1.30 gl1l5ms140s 1.40 gl1l5ms150s 1.50 <2.0 ohm gl1l5ms160s 1.60 gl1l5ms170s 1.70 gl1l5ms180s 1.80 gl1l5ms190s 1.90 >1.50 ghz <400 ps <400 ps gl1l5ms200s 2.00 gl1l5ms210s 2.10 gl1l5ms220s 2.20 gl1l5ms230s 2.30 gl1l5ms240s 2.40 gl1l5ms250s 2.50 <3.0 ohm gl1l5ms260s 2.60 gl1l5ms270s 2.70 gl1l5ms280s 2.80 gl1l5ms290s 2.90 gl1l5ms300s 3.00 >1.00 ghz gl1l5ms310s 3.10 gl1l5ms320s 3.20 gl1l5ms330s 3.30 gl1l5ms340s 3.40 gl1l5ms350s 3.50 <4.0 ohm gl1l5ms360s 3.60 gl1l5ms370s 3.70 gl1l5ms380s 3.80 <600 ps <600 ps gl1l5ms390s 3.90 gl1l5ms400s 4.00 gl1l5ms410s 4.10 >0.75 ghz gl1l5ms420s 4.20 gl1l5ms430s 4.30 gl1l5ms440s 4.40 gl1l5ms450s 4.50 <5.0 ohm gl1l5ms460s 4.60 gl1l5ms470s 4.70 >0.50 ghz gl1l5ms480s 4.80 gl1l5ms490s 4.90 gl1l5ms500s 5.00 p/n td insertion loss return loss tro tfo dcrv (ns) (-3 db) (15 db) dimension mm application note: save time with board layout and maintain flexibility with your clock dis- tribution network. design in a smt delay line and avoid timely and costly board revisions. !
gl1 s gl1 s eries d d elay l l ines gl1l5 ** *** s u.s. patent 5,365,203 s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 1. 742 ghz 1 1 - 3. 218 db 1 1 - 14. 994 db m arker 1 0. 969 ghz s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 1. 167 ghz 1 1 - 2. 977 db 1 1 - 14. 942 db 1. 367 ghz m arker 1 s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 0. 892 ghz 1 1 - 3. 008 db 1 1 - 13. 937 db 1. 647 ghz m arker 1 s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 0. 592 ghz 1 1 - 2. 995 db 1 1 - 14. 275 db m arker 1 1. 191 ghz gl1l5ms300s 3 ns gl1l5ms400s 4 ns gl1l5ms500s 5 ns s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 2. 931 ghz 1 1 - 2. 997 db 1 1 - 15. 000 db m arker 1 0. 949 ghz gl1l5ls100s 1 ns gl1l5ms200s 2 ns characterization data is typical for this series of delay lines.
gl2 s gl2 s eries d d elay l l ines gl2l5 ** ***d u.s. patent 5,815,050 application note: apply to positive emitter coupled logic (pecl) or other differentially driven circuits to produce a precisely cotrolled clock distribution network (see page 17). ! ms190d m 6.05 max 8.35 max 13.55 max 1.88 0.25 1.27 0.13 5.15 max 0.56 max 18 0.28 0.05 0.10 1 8 9 16 gl2l5 series 50 ohm GL2L5LS050D 0.50 >1.80 ghz >0.60 ghz <400 ps <400 ps <1.0 ohm gl2l5ls100d 1.00 gl2l5ms150d 1.50 >0.80 ghz <2.0 ohm gl2l5ms200d 2.00 gl2l5ms250d 2.50 >0.45 ghz <3.0 ohm gl2l5ms300d 3.00 <800 ps <800 ps gl2l5ms350d 3.50 <4.0 ohm gl2l5ms400d 4.00 >0.25 ghz gl2l5ms450d 4.50 <5.0 ohm p/n td insertion loss return loss tro tfo dcrv (ns) (-3 db) (15 db) dimension mm
s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 1. 867 ghz 1 1 - 3. 020 db 1 1 - 15. 072 db m arker 1 1. 731 ghz s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 1. 974 ghz 1 1 - 3. 001 db 1 1 - 15. 004 db m arker 1 1. 041 ghz s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / 0. 446 ghz 1 1 - 3. 072 db 1 1 - 14. 823 db 0. 754 ghz m arker 1 m arker 1 GL2L5LS050D 0.5 ns gl2l5ls100d 1 ns s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 0. 845 ghz 1 1 - 2. 998 db 1 1 - 14. 986 db m arker 1 1. 666 ghz gl2l5ms200d 2 ns gl2l5ms300d 3 ns characterization data is typical for this series of delay lines. gl2 s gl2 s eries d d elay l l ines gl2l5 ** ***d u.s. patent 5,815,050
ds s ds s eries d d elay l l ines ds1l5 ** *** s u.s. patent 4,641,113 6.35 max 3.20 min 0.25 0.50 0.10 2.54 3.86 12.40 max 200 m max 0.10 ds1l5 series 50 ohm ds1l5dj010s 0.10 >1.000 >1.000 <0.10 ds1l5dj020s 0.20 0.900 0.750 0.20 ds1l5dj030s 0.30 0.700 0.650 0.30 ds1l5dj040s 0.40 0.650 0.475 <0.50 <0.50 0.40 ds1l5dj050s 0.50 0.600 0.450 0.50 ds1l5dj060s 0.60 0.550 0.375 0.60 ds1l5dj070s 0.70 0.500 0.350 0.70 ds1l5dj080s 0.80 0.500 0.300 0.80 ds1l5dj090s 0.90 1.200 0.50 0.50 ds1l5dj100s 1.00 1.100 0.300 0.55 0.55 0.25 ds1l5dj110s 1.10 1.000 0.60 0.60 ds1l5dj120s 1.20 1.000 0.65 0.65 ds1l5dj130s 1.30 0.950 0.275 0.70 0.70 0.30 ds1l5dj140s 1.40 0.900 0.75 0.75 ds1l5dj150s 1.50 0.850 0.80 0.80 ds1l5dj160s 1.60 0.800 0.85 0.85 0.50 ds1l5dj170s 1.70 0.750 0.250 0.90 0.90 ds1l5dj180s 1.80 0.700 0.95 0.95 ds1l5dj190s 1.90 0.650 1.00 1.00 0.70 ds1l5dj200s 2.00 0.600 0.550 1.05 1.05 ds1l5dj225s 2.25 0.550 0.500 1.10 1.10 ds1l5dj250s 2.50 0.500 0.450 1.25 1.25 ds1l5dj275s 2.75 0.450 0.400 1.35 1.35 1.00 ds1l5dj300s 3.00 0.400 0.300 1.45 1.45 ds1l5dj325s 3.25 0.550 1.10 ds1l5dj350s 3.50 1.00 1.00 1.20 ds1l5dj375s 3.75 0.450 0.250 1.30 ds1l5dj400s 4.00 1.40 ds1l5dj425s 4.25 0.425 1.50 ds1l5dj450s 4.50 1.10 1.10 1.60 ds1l5dj475s 4.75 0.400 1.70 ds1l5dj500s 5.00 0.225 1.80 ds1l5vj550s 5.50 0.375 2.00 ds1l5vj600s 6.00 0.350 1.15 1.15 2.20 p/n td insertion loss return loss tro tfo dcrv (ns) ghz (-3 db) ghz (15 db) (ns) (ns) (ohm) application note: use the ds delay lines in series with the gl2 delay line during board prototype to define the required timing delay. ! dimension mm
ds s ds s eries d d elay l l ines ds1l5 ** *** s u.s. patent 4,641,113 s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 1. 500 ghz s 11 l og mag ref 0 db 10 db / m arker 1 1. 203 ghz 1 1 - 2. 993 db 1 1 - 14. 999 db m arker 1 0. 295 ghz s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 1. 500 ghz s 11 l og mag ref 0 db 10 db / m arker 1 638 mhz 1 1 - 2. 986 db 1 1 - 15. 015 db m arker 1 553 mhz s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 1. 500 ghz s 11 l og mag ref 0 db 10 db / m arker 1 389 mhz 1 1 - 2. 999 db 1 1 - 15. 001 db m arker 1 312 mhz s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 1. 500 ghz s 11 l og mag ref 0 db 10 db / m arker 1 486 mhz 1 1 - 2. 996 db 1 1 - 14. 999 db m arker 1 263 mhz s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 1. 500 ghz s 11 l og mag ref 0 db 10 db / m arker 1 436 mhz 1 1 - 3. 042 db 1 1 - 14. 954 db m arker 1 239 mhz ds1l5dj100s 1 ns ds1l5dj200s 2 ns ds1l5dj300s 3 ns ds1l5dj400s 4 ns ds1l5dj500s 5 ns characterization data is typical for this series of delay lines.
cl cl s s eries d d elay l l ines cl1l52h*** s u.s. patent 5,808,241 2.5 0.2 3.2 0.2 0.5 max 1 2 3 4 1 2 3 4 x 0 2 x s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 2. 959 ghz 1 1 - 3. 000 db 1 1 - 14. 999 db m arker 1 2. 081 ghz s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 1. 868 ghz 1 1 - 3. 000 db 1 1 - 15. 000 db m arker 1 0. 566 ghz s 21 l og mag 5 db / ref 0 db start . 050 ghz sto p 6. 000 ghz s 11 l og mag ref 0 db 10 db / m arker 1 1. 868 ghz 1 1 - 3. 000 db 1 2 - 14. 999 db m arker 1 0. 565 ghz cl1l52h002s 0.02 ns cl1l52h016s 0.16 ns cl1l52h020s 0.20 ns application note: use for ultra-precise delay adjustments where circuit trace is nearly adequate on the smallest of boards. use for phase-locked loop timing schemes. ! cl1l5 series 50 ohm cl1l52h002s 20 2.4 0.600 cl1l52h004s 40 2.3 <10 <10 <0.30 cl1l52h006s 60 2.2 cl1l52h008s 80 2.1 cl1l52h010s 100 2.0 cl1l52h012s 120 1.9 cl1l52h014s 140 1.8 cl1l52h016s 160 1.7 20 20 0.60 cl1l52h018s 180 1.6 cl1l52h020s 200 1.5 p/n td insertion loss return loss tro tfo dcrv (ps) ghz(-3 db) ghz(15 db) (ps) (ps) (ohm)
b b andwidth c c onsiderations h h igh frequency signals with fast rise and fall times can push circuit elements to their limit in high speed digital design. below illustrates what happens in the relationship between a random digital pulse train and the important part of the frequency spectrum when an output is flip-flop clocked at a rate of f clock with a risetime t r that is 1% of the clock period. the plotted spectral power density displays nulls at multiples of the clock rate and an overall -20db/decade slope from f clock up to f knee , where the roll off is faster. the knee frequency for a digital signal is related to the rise and fall times, not the clock rate: f knee = , f knee = the frequency which most energy in digital pulses concentrates t r = pulse rise time 0 -20 -40 -60 -80 -100 dbv nulls at multiples of the clock rate clock rate knee frequency 20 db/decade straight slope up to the knee frequency frequency relative to clock rate 0.1 1.0 10.0 100.0 1000.0 0.5 tr
c c omplimentary p p roduct differential terminator rn1632n1dnc 1.0 0.2 0.4 0.25 3.2 0.2 1.6 0.2 top 0.4 0.2 bottom 1 2 3 0.4 0.1 1 3 2 differential fan out buffer differential delay line differential signal ?in? clock distribution network example using gl2l delay line and rn1632 t erminators differential terminators differential signal ?out? r1= 50.0 ohm r2 = 46.4 ohm r3 = 50.0 ohm t t his standard 1206 size chip resistor network is popular for positive emitter coupled logic (pecl) applications as a terminator. because this single chip contains three resis- tors, it reduces pick and place actions from three to one. gl2l
c c omplimentary p p roducts slot sets pskt***n* 7.10 3.00 5.24 2.82 1.50 0.62 9.30 5.72 0.63 1.20 0.60 0.345 pad t t ypical high frequency calibration routines call for a series of nulling procedures that use electrical shorts, opens, loads, and throughs that are connected to the cable ends that feed the test instrument. these will effectively null out undesired matching, loading, frequency response, etc., of the test sys- tem to the cable ends. however, the device under test (dut) requires a socket or fixture to mate with the cable connector. the actual measurement taken includes both the dut and the test fixture. the pskt***n* series calibration standards are for de-embedding the test fixture effects in these high speed measurements, because the calibration routine is performed at the test fixture. essentially a custom set of products containing an electrical short, open, load, and through, specifically designed for the targeted schematic, these are used during the cali- bration routine with a network analyzer or other high speed test equipment. the end result is that the device under test performance is more accurate. available in sip and dip form factors, these calibration standards have gold finished elec- trodes and are intended for surface mount applications. short open thru load
f f ootprint l l ayouts gl1l gl1l and gl2l gl2l s s eries cl1l cl1l s s eries 1.27 pitch 0.72 1.80 7.48 9.68 6.08 dimensions in mm the above land dimensions are suggested for the surface mount products gl1l/gl2l and cl1l series delay lines. optimized geometries will vary depending on assembly process parameters. since each assembly engineer is familiar with character unique to their process, these dimensions are a starting point, not to be recognized as a definitive solution.
t t hin f f ilm t t echnology 1980 c c ommerce d d rive n n orth m m ankato, m m innesota 56003 507 625-8445 507 625-3523 facsimile http://www.thin-film.com because because t t iming is everything. iming is everything. tm tm

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